oxidecomputer / oxidecomputer/quartz

sidecar FPGA needs to provide a method of clearing out the TX FIFO registers

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#447 0 comments 0 reactions 1 assignee View on GitHub

@Aaron-Hartwig is already working on this.

Since Jan 13, 2026.

Dominant language
VHDL
Stars
22
Forks
2
Avg merge
9h 38m
Merged PRs (30d)
1

Description

see https://github.com/oxidecomputer/hubris/issues/2326 for description of the fallout here. This register is reported as ReadOnly so we need something here to allow this to be cleared or change the design such that a NACK doesn't strand bytes in an un-clearable FIFO

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