oxidecomputer / oxidecomputer/quartz
Extra sclk inserted before a STOP by i2c link layer
Open
Nobody has claimed this yet.
- Dominant language
- VHDL
- Stars
- 22
- Forks
- 2
- Avg merge
- 9h 38m
- Merged PRs (30d)
- 1
Description
Since we've NACK'd on reads or are doing writes, this is benign in that it causes no bad behavior but is incorrect.
Red marker is the ACK phase. Green marker is the CLK high period where the STOP should be generated but instead it is generated at the next clock.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the I2C link layer's STOP generation and compare its behavior with the attached waveform, focusing on the ACK phase and the extra clock before STOP. Done means the STOP is generated during the indicated clock-high period rather than on the next clock, without inserting an extra SCLK.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100