QsfpModuleController does not clear it's read buffer when starting a new transaction

While investigating an unrelated transceiver problem I realized I could wedge the module I2C communications by issuing back-to-back 128-byte reads without draining the read data buffers in between (like all the software does).

Once the second read begins, the I2CCore doesn't have anywhere to put the data it is reading since the underlying buffer in the QsfpModuleController is a FIFO interface to a BRAM. This is likely the root cause of https://github.com/oxidecomputer/hubris/issues/2070, although I'm not sure how it would've happened unless someone was manually poking FPGA registers since our software drains these buffers as part of the higher level read operation. Anyway, knowing this also gives a convenient way to test a resolution for https://github.com/oxidecomputer/quartz/issues/362 before I fix this particular issue.