ram inferrence improvements

I'd like to work out a better solution in the following areas:

• Mixed width FIFOs. These behave strangely in some cases (write side > read side) and we may not be properly meeting the vivado rules of only using "auto" when the sizes are matched.
• in the mixed DPR config, when write side > read_side I needed to register the read output in order for the ram to be picked up correctly by vivado.
• We don't have SCFIFOs wrapped right now

I need to spend some more time investigating this and working out a better solution to these things, ideally one more platform independent or wrapped in an independent way

Start by tracing the mixed-width FIFO and mixed DPR RAM configurations and reviewing how Vivado RAM inference is currently handled. Investigate the output-registration requirement for write-side width greater than read-side width, and examine the absence of SCFIFOs. Done means the behavior is understood and a platform-independent solution is defined for these cases.