espi: phy timing, quad I/O testing

For now, the design is running x1 and advertises 20MHz support only

I need to do proper I/O timing constraints here to support maximum speeds. After evaluating the AMD timing parameters and our board delays I'm going to have to slightly re-tool the phy layer to run on the espi clock directly rather than at 200MHz so that we can hit the I/O delay perf we need.

This was a known possibility when I re-tooled the phy layer from the most naive original implementation, but there are a number of domain crossings and things that need to be carefully managed here and documentation updated. Since this is an enhancement vs core functionality it's been de-prioritized in favor of work to get interfaces which have no implementation up and running.

Start by reviewing the PHY layer and the existing x1, 20MHz design, then evaluate the AMD timing parameters and board delays mentioned in the issue. The work is done when maximum-speed I/O timing constraints and quad I/O testing are supported, domain crossings are managed, and the documentation is updated.