Would like top-level decode packages from top-level RDLs

We'll often have top level .rdl files that provide the FPGA memory map ala:

addrmap top_level_map {
    default regwidth = 32;
    // Instantiate 2 to test nesting
    gfruit_base_regs base @ 0x0;
    nor_flash_regs spi_nor @ 0x0100;
    espi_regs espi @ 0x0200;
    gfruit_sgpio sgpio @ 0x0300;
};

For the VHDL flow, the user needs to manually generate some config constants and signals like:

 constant config_array : axil_responder_cfg_array_t := 
     (0 => (base_addr => x"00000000", addr_span_bits => 8),
      1 => (base_addr => x"00000100", addr_span_bits => 8),
      2 => (base_addr => x"00000200", addr_span_bits => 8),
      3 => (base_addr => x"00000300", addr_span_bits => 8)
      );
    signal responders : axil8x32_pkg.axil_array_t(config_array'range);

It would be nice to auto-generate a package that includes this kind of information and can just be pulled in. This would also have the benefit of needing to update the top-level map when implementing new peripherals.

Start by tracing the VHDL flow that currently requires manually written config_array constants and responder signals, alongside the top-level .rdl map shown in the issue. Done means a generated package exposes the memory-map information for direct inclusion and reflects newly added peripherals through the top-level map.