oxidecomputer / oxidecomputer/quartz
SPI: Increase response time for reads
Nobody has claimed this yet.
- Dominant language
- VHDL
- Stars
- 22
- Forks
- 2
- Avg merge
- 9h 38m
- Merged PRs (30d)
- 1
Description
Currently when a READ command is issued, data must be supplied the next clock cycle. This works fine for data that is sitting in registers somewhere already, but it does not give time to fetch data from RAMs. What type of solution do we want here? A flat increase in number of cycles? Or perhaps a dynamic latency depending on the type of access?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue concerns SPI READ command timing and fetching data from RAMs, but names no files, tests, or entry points. First locate the SPI implementation and its timing tests, then determine whether fixed or dynamic latency is intended. Done means the chosen latency behavior supports RAM reads and is covered by tests.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100