must disable automatic link speed and width changes during margining

Per the PCIe spec section 4.2.13.3, the following conditions must be true before margining:

• The current Link data rate must be 16.0 GT/s or higher.
• The current Link width must include the Lanes that are to be tested.
• The Upstream Port's Function(s) must be programmed to a D-state that prevents the Port from entering the L1
Link state. See Section 5.2 for more information.
• The ASPM Control field of the Link Control register must be set to 00b (Disabled) in both the Downstream Port
and Upstream Port.
• The state of the Hardware Autonomous Speed Disable bit of the Link Control 2 register and the Hardware
Autonomous Width Disable bit of the Link Control register must be saved to be restored later in this procedure.
• If writeable, the Hardware Autonomous Speed Disable bit of the Link Control 2 register must be Set in both the
Downstream Port and Upstream Port. (If hardwired to 0b, the autonomous speed change mechanism is not
implemented and is therefore inherently disabled.)
• If writeable, the Hardware Autonomous Width Disable bit of the Link Control register must be Set in both the
Downstream Port and Upstream Port. (If hardwired to 0b, the autonomous width change mechanism is not
implemented and is therefore inherently disabled.)

I am not sure about the D-state part, but I believe we are not setting the Hardware Autonomous Speed Disable or the Hardware Autonomous Width Disable bits of the Link, Control registers. I didn't find any reference to them or the address offsets for the registers they are contained in in main.rs

Here are the registers for those two settings. Note: Existing settings for these should be restored upon a completion or failure of margining.

Link Control Register (offset 0x10), Bit 9 - Hardware Autonomous Width Disable, Set to 1
Link Control 2 Register (offset 0x30), Bit 5 - Hardware Autonomous Speed Disable, Set to 1

Though we don't implement any low power states for PCIe, we should ensure the ASPM Control is set to 0x0 as well. ASPM Control is in bits 0 and 1 of the Link Control Register (offset 0x10)

Start in main.rs and trace the PCIe lane-margining setup and cleanup paths. Check how Link Control and Link Control 2 registers are accessed, then verify how saved values would be restored after both completion and failure. The PCIe margining flow should cover the specified ASPM and autonomous speed/width settings.