oxidecomputer / oxidecomputer/lmar

margining downstream ports

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Description

so it's captured, here is an attempt to margin upstream and downstream on a gen4 port:

BRM42220038 # /usr/lib/pci/pcieadm show-devs
BDF     TYPE           INSTANCE       DEVICE
40/3/3  PCIe Gen 4x4   pcieb11        Starship/Matisse GPP Bridge
48/0/0  PCIe Gen 4x4   nvme6          NVMe SSD Controller PM9A1/PM9A3/980PRO

BRM42220038 # /tmp/lmar 48/0/0 upstream -v -v
LinkStatus {
    speed: LinkSpeed(
        16.0,
    ),
    width: LinkWidth(
        0x4,
    ),
    training: false,
    active: false,
}
ReportCapabilities {
    independent_error_sampler: true,
    sample_reporting_method: Count,
    independent_left_right_sampling: true,
    independent_up_down_voltage: true,
    voltage_supported: true,
}
MarginingLimits {
    num_voltage_steps: Some(
        127,
    ),
    num_timing_steps: 31,
    max_timing_offset: 50,
    max_voltage_offset: Some(
        30,
    ),
    sampling_rate_voltage: Some(
        0,
    ),
    sampling_rate_timing: 0,
}
Margin duration 1s
Writing results to: "margin-results-b48-d0-f0-l0-1986-12-28T00-16-09.txt"
1/62: StepLeftRight { direction: Some(Left), steps: Steps(31) }, Duration: 1.008725ms, Failed(ErrorCount(31))
2/62: StepLeftRight { direction: Some(Left), steps: Steps(30) }, Duration: 1.008765ms, Failed(ErrorCount(31))
3/62: StepLeftRight { direction: Some(Left), steps: Steps(29) }, Duration: 1.008525ms, Failed(ErrorCount(31))
4/62: StepLeftRight { direction: Some(Left), steps: Steps(28) }, Duration: 1.008745ms, Failed(ErrorCount(31))
5/62: StepLeftRight { direction: Some(Left), steps: Steps(27) }, Duration: 1.008575ms, Failed(ErrorCount(31))
6/62: StepLeftRight { direction: Some(Left), steps: Steps(26) }, Duration: 1.008526ms, Failed(ErrorCount(31))
7/62: StepLeftRight { direction: Some(Left), steps: Steps(25) }, Duration: 1.008816ms, Failed(ErrorCount(31))
8/62: StepLeftRight { direction: Some(Left), steps: Steps(24) }, Duration: 1.009025ms, Failed(ErrorCount(23))
9/62: StepLeftRight { direction: Some(Left), steps: Steps(23) }, Duration: 1.008555ms, Failed(ErrorCount(23))
10/62: StepLeftRight { direction: Some(Left), steps: Steps(22) }, Duration: 1.008515ms, Failed(ErrorCount(16))
11/62: StepLeftRight { direction: Some(Left), steps: Steps(21) }, Duration: 1.008646ms, Failed(ErrorCount(6))
12/62: StepLeftRight { direction: Some(Left), steps: Steps(20) }, Duration: 1.008636ms, Failed(ErrorCount(5))
13/62: StepLeftRight { direction: Some(Left), steps: Steps(19) }, Duration: 1.008945ms, Failed(ErrorCount(5))
14/62: StepLeftRight { direction: Some(Left), steps: Steps(18) }, Duration: 1.008545ms, Failed(ErrorCount(5))
15/62: StepLeftRight { direction: Some(Left), steps: Steps(17) }, Duration: 1.002032738s, Failed(ErrorCount(5))
16/62: StepLeftRight { direction: Some(Left), steps: Steps(16) }, Duration: 1.002031528s, Failed(ErrorCount(5))
17/62: StepLeftRight { direction: Some(Left), steps: Steps(15) }, Duration: 1.002035458s, Failed(ErrorCount(5))
18/62: StepLeftRight { direction: Some(Left), steps: Steps(14) }, Duration: 1.002031398s, Failed(ErrorCount(5))
19/62: StepLeftRight { direction: Some(Left), steps: Steps(13) }, Duration: 1.006073499s, Success(ErrorCount(0))
^C
BRM42220038 # /tmp/lmar 40/3/3 upstream -v -v
LinkStatus {
    speed: LinkSpeed(
        16.0,
    ),
    width: LinkWidth(
        0x4,
    ),
    training: false,
    active: true,
}
Error: Could not initialize lane margining

Caused by:
    An error occurred during lane margining: margining failed, did not find expected response for command Report(Capabilities) within time limit of 10ms: Ok(Empty)
BRM42220038 # /tmp/lmar 40/3/3 downstream -v -v
LinkStatus {
    speed: LinkSpeed(
        16.0,
    ),
    width: LinkWidth(
        0x4,
    ),
    training: false,
    active: true,
}
ReportCapabilities {
    independent_error_sampler: false,
    sample_reporting_method: Count,
    independent_left_right_sampling: false,
    independent_up_down_voltage: false,
    voltage_supported: false,
}
MarginingLimits {
    num_voltage_steps: None,
    num_timing_steps: 0,
    max_timing_offset: 0,
    max_voltage_offset: None,
    sampling_rate_voltage: None,
    sampling_rate_timing: 0,
}
Margin duration 1s
Writing results to: "margin-results-b40-d3-f3-l0-1986-12-28T00-16-52.txt"
BRM42220038 # /tmp/lmar 48/0/0 downstream -v -v
LinkStatus {
    speed: LinkSpeed(
        16.0,
    ),
    width: LinkWidth(
        0x4,
    ),
    training: false,
    active: false,
}
Error: Could not initialize lane margining

Caused by:
    An error occurred during lane margining: margining failed, did not find expected response for command Report(Capabilities) within time limit of 10ms: Ok(StepExecutionStatus {)

When we dump the register space for the M2A:

BRM42220038 # /tmp/dumpregs.sh M2A
                           PCIECORE::PCIE_HW_DEBUG (0x11480008) = 0x0
                        PCIECORE::PCIE_HW_DEBUG_LC (0x1148000c) = 0x0
                         PCIECORE::PCIE_RX_NUM_NAK (0x11480038) = 0x0
               PCIECORE::PCIE_RX_NUM_NAK_GENERATED (0x1148003c) = 0x0
                               PCIECORE::PCIE_CNTL (0x11480040) = 0x80a11000
                        PCIECORE::PCIE_CONFIG_CNTL (0x11480044) = 0xf
                         PCIECORE::PCIE_DEBUG_CNTL (0x11480048) = 0x1
                              PCIECORE::PCIE_CNTL2 (0x11480070) = 0xe004109
                           PCIECORE::PCIE_RX_CNTL2 (0x11480074) = 0x0
                    PCIECORE::PCIE_TX_F0_ATTR_CNTL (0x11480078) = 0x0
                            PCIECORE::PCIE_CI_CNTL (0x11480080) = 0xe0000050
                           PCIECORE::PCIE_BUS_CNTL (0x11480084) = 0x0
                          PCIECORE::PCIE_LC_STATE6 (0x11480088) = 0x0
                          PCIECORE::PCIE_LC_STATE7 (0x1148008c) = 0x0
                          PCIECORE::PCIE_LC_STATE8 (0x11480090) = 0x0
                          PCIECORE::PCIE_LC_STATE9 (0x11480094) = 0x0
                         PCIECORE::PCIE_LC_STATE10 (0x11480098) = 0x0
                         PCIECORE::PCIE_LC_STATE11 (0x1148009c) = 0x0
                         PCIECORE::PCIE_LC_STATUS1 (0x114800a0) = 0x90
                         PCIECORE::PCIE_LC_STATUS2 (0x114800a4) = 0x190000
                           PCIECORE::PCIE_TX_CNTL3 (0x114800a8) = 0x1808c0
                          PCIECORE::PCIE_TX_STATUS (0x114800ac) = 0xf3f
                           PCIECORE::PCIE_WPR_CNTL (0x114800c0) = 0x5
                       PCIECORE::PCIE_RX_LAST_TLP0 (0x114800c4) = 0x0
                       PCIECORE::PCIE_RX_LAST_TLP1 (0x114800c8) = 0x0
                       PCIECORE::PCIE_RX_LAST_TLP2 (0x114800cc) = 0x0
                       PCIECORE::PCIE_RX_LAST_TLP3 (0x114800d0) = 0x0
                       PCIECORE::PCIE_TX_LAST_TLP0 (0x114800d4) = 0x0
                       PCIECORE::PCIE_TX_LAST_TLP1 (0x114800d8) = 0x0
                       PCIECORE::PCIE_TX_LAST_TLP2 (0x114800dc) = 0x0
                       PCIECORE::PCIE_TX_LAST_TLP3 (0x114800e0) = 0x0
                PCIECORE::PCIE_I2C_REG_ADDR_EXPAND (0x114800e8) = 0x0
                       PCIECORE::PCIE_I2C_REG_DATA (0x114800ec) = 0x0
                           PCIECORE::PCIE_CFG_CNTL (0x114800f0) = 0x0
                         PCIECORE::PCIE_LC_PM_CNTL (0x114800f4) = 0x76543210
                 PCIECORE::PCIE_LC_PORT_ORDER_CNTL (0x114800f8) = 0x1
                             PCIECORE::PCIE_P_CNTL (0x11480100) = 0x854040
                       PCIECORE::PCIE_P_BUF_STATUS (0x11480104) = 0x0
                   PCIECORE::PCIE_P_DECODER_STATUS (0x11480108) = 0x0
                      PCIECORE::PCIE_P_MISC_STATUS (0x1148010c) = 0x0
                       PCIECORE::PCIE_P_RX_L0S_FTS (0x11480140) = 0xff
                      PCIECORE::PCIE_TX_CCIX_CNTL0 (0x11480150) = 0x8
                      PCIECORE::PCIE_TX_CCIX_CNTL1 (0x11480154) = 0x1002
                   PCIECORE::PCIE_TX_CCIX_PORT_MAP (0x11480158) = 0x10
                    PCIECORE::PCIE_TX_CCIX_ERR_CTL (0x1148015c) = 0x0
                       PCIECORE::PCIE_RX_CCIX_CTL0 (0x11480160) = 0xf1400
                              PCIECORE::PCIE_RX_AD (0x11480188) = 0x3
                           PCIECORE::PCIE_SDP_CTRL (0x1148018c) = 0x2
              PCIECORE::PCIE_NBIO_CLKREQb_MAP_CNTL (0x11480190) = 0x0
               PCIECORE::PCIE_SDP_RC_SLV_ATTR_CTRL (0x11480198) = 0x0
                           PCIECORE::PCIE_STRAP_F0 (0x114802c0) = 0x8014e065
                          PCIECORE::PCIE_STRAP_NTB (0x114802c4) = 0x8004
                         PCIECORE::PCIE_STRAP_MISC (0x11480300) = 0xa0000007
                        PCIECORE::PCIE_STRAP_MISC2 (0x11480304) = 0x3f
                           PCIECORE::PCIE_STRAP_PI (0x11480308) = 0x0
                           PCIECORE::PCIE_PRBS_CLR (0x11480320) = 0x0
                       PCIECORE::PCIE_PRBS_STATUS1 (0x11480324) = 0x0
                       PCIECORE::PCIE_PRBS_STATUS2 (0x11480328) = 0x0
                       PCIECORE::PCIE_PRBS_FREERUN (0x1148032c) = 0x0
                          PCIECORE::PCIE_PRBS_MISC (0x11480330) = 0x0
                  PCIECORE::PCIE_PRBS_USER_PATTERN (0x11480334) = 0x0
                     PCIECORE::PCIE_PRBS_LO_BITCNT (0x11480338) = 0x0
                     PCIECORE::PCIE_PRBS_HI_BITCNT (0x1148033c) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT0 (0x11480340) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT1 (0x11480344) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT2 (0x11480348) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT3 (0x1148034c) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT4 (0x11480350) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT5 (0x11480354) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT6 (0x11480358) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT7 (0x1148035c) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT8 (0x11480360) = 0x0
                       PCIECORE::PCIE_PRBS_ERRCNT9 (0x11480364) = 0x0
                      PCIECORE::PCIE_PRBS_ERRCNT10 (0x11480368) = 0x0
                      PCIECORE::PCIE_PRBS_ERRCNT11 (0x1148036c) = 0x0
                      PCIECORE::PCIE_PRBS_ERRCNT12 (0x11480370) = 0x0
                      PCIECORE::PCIE_PRBS_ERRCNT13 (0x11480374) = 0x0
                      PCIECORE::PCIE_PRBS_ERRCNT14 (0x11480378) = 0x0
                      PCIECORE::PCIE_PRBS_ERRCNT15 (0x1148037c) = 0x0
                    PCIECORE::SWRST_COMMAND_STATUS (0x11480400) = 0x30000
                   PCIECORE::SWRST_GENERAL_CONTROL (0x11480404) = 0x2001003
                         PCIECORE::SWRST_COMMAND_0 (0x11480408) = 0x0
                         PCIECORE::SWRST_COMMAND_1 (0x1148040c) = 0x0
                         PCIECORE::SWRST_CONTROL_0 (0x11480410) = 0x5600ff00
                         PCIECORE::SWRST_CONTROL_1 (0x11480414) = 0xc220ffff
                         PCIECORE::SWRST_CONTROL_2 (0x11480418) = 0x0
                         PCIECORE::SWRST_CONTROL_3 (0x1148041c) = 0x0
                         PCIECORE::SWRST_CONTROL_4 (0x11480420) = 0x5c00ff01
                         PCIECORE::SWRST_CONTROL_5 (0x11480424) = 0xfe20ffff
                         PCIECORE::SWRST_CONTROL_6 (0x11480428) = 0x7fb
                             PCIECORE::CPM_CONTROL (0x11480460) = 0x80ca00
                       PCIECORE::CPM_SPLIT_CONTROL (0x11480464) = 0x0
                          PCIECORE::SMN_APERTURE_A (0x11480474) = 0x0
                          PCIECORE::SMN_APERTURE_B (0x11480478) = 0x0
                     PCIECORE::RSMU_MASTER_CONTROL (0x1148047c) = 0x0
                      PCIECORE::RSMU_SLAVE_CONTROL (0x11480480) = 0x1
               PCIECORE::RSMU_POWER_GATING_CONTROL (0x11480484) = 0x0
                     PCIECORE::RSMU_BIOS_TIMER_CMD (0x11480488) = 0x6d2c23c2
                    PCIECORE::RSMU_BIOS_TIMER_CNTL (0x1148048c) = 0x64
                   PCIECORE::RSMU_BIOS_TIMER_DEBUG (0x11480490) = 0x0
                           PCIECORE::LNCNT_CONTROL (0x11480494) = 0x6
                         PCIECORE::LNCNT_QUAN_THRD (0x1148049c) = 0x33
                            PCIECORE::LNCNT_WEIGHT (0x114804a0) = 0x0
                    PCIECORE::SMU_HP_STATUS_UPDATE (0x114804b0) = 0x50011
                   PCIECORE::HP_SMU_COMMAND_UPDATE (0x114804b4) = 0x0
                 PCIECORE::SMU_HP_END_OF_INTERRUPT (0x114804b8) = 0x0
      PCIECORE::SMU_INT_PIN_SHARING_PORT_INDICATOR (0x114804bc) = 0x400
                         PCIECORE::PCIE_PGMST_CNTL (0x114804c0) = 0x0
                         PCIECORE::PCIE_PGSLV_CNTL (0x114804c4) = 0x4
                     PCIECORE::SMU_PCIE_DF_Address (0x114804c8) = 0x0
                        PCIECORE::LC_CPM_CONTROL_0 (0x114804cc) = 0x0
                        PCIECORE::LC_CPM_CONTROL_1 (0x114804d0) = 0x1
      PCIECORE::PCIE_RXMARGIN_CONTROL_CAPABILITIES (0x114804d4) = 0x0
                PCIECORE::PCIE_RXMARGIN_1_SETTINGS (0x114804d8) = 0x0
                PCIECORE::PCIE_RXMARGIN_2_SETTINGS (0x114804dc) = 0x0
             PCIECORE::PCIE_PRESENCE_DETECT_SELECT (0x114804e0) = 0x404
                      PCIECORE::PCIE_LC_DEBUG_CNTL (0x114804e4) = 0x10000
                    PCIECORE::SMU_PCIE_FENCED1_REG (0x11480600) = 0x0
                    PCIECORE::SMU_PCIE_FENCED2_REG (0x11480604) = 0x0
                          PCIEPORT::PCIEP_HW_DEBUG (0x11442008) = 0x8000
                       PCIEPORT::PCIEP_HW_DEBUG_LC (0x1144200c) = 0x0
                         PCIEPORT::PCIEP_PORT_CNTL (0x11442040) = 0x2000019
                          PCIEPORT::PCIEP_SDP_CTRL (0x11442044) = 0x0
                            PCIEPORT::PCIE_TX_CNTL (0x11442080) = 0x500000
                    PCIEPORT::PCIE_TX_REQUESTER_ID (0x11442084) = 0xb
                 PCIEPORT::PCIE_TX_VENDOR_SPECIFIC (0x11442088) = 0x0
                PCIEPORT::PCIE_TX_REQUEST_NUM_CNTL (0x1144208c) = 0x2000000
                             PCIEPORT::PCIE_TX_SEQ (0x11442090) = 0x1c901ca
                          PCIEPORT::PCIE_TX_REPLAY (0x11442094) = 0x480003
               PCIEPORT::PCIE_TX_ACK_LATENCY_LIMIT (0x11442098) = 0x100c
                        PCIEPORT::PCIE_TX_NOP_DLLP (0x1144209c) = 0x0
                          PCIEPORT::PCIE_TX_CNTL_2 (0x114420a0) = 0x4
                  PCIEPORT::PCIE_TX_CREDITS_ADVT_P (0x114420c0) = 0x4001fc
                 PCIEPORT::PCIE_TX_CREDITS_ADVT_NP (0x114420c4) = 0x400000
                PCIEPORT::PCIE_TX_CREDITS_ADVT_CPL (0x114420c8) = 0x20007c
                  PCIEPORT::PCIE_TX_CREDITS_INIT_P (0x114420cc) = 0x200100
                 PCIEPORT::PCIE_TX_CREDITS_INIT_NP (0x114420d0) = 0x200020
                PCIEPORT::PCIE_TX_CREDITS_INIT_CPL (0x114420d4) = 0x7f0201
                  PCIEPORT::PCIE_TX_CREDITS_STATUS (0x114420d8) = 0x0
           PCIEPORT::PCIE_TX_CREDITS_FCU_THRESHOLD (0x114420dc) = 0x3330333
                 PCIEPORT::PCIE_TX_CCIX_PORT_CNTL0 (0x114420e0) = 0xb
                 PCIEPORT::PCIE_TX_CCIX_PORT_CNTL1 (0x114420e4) = 0x0
                  PCIEPORT::PCIE_CCIX_STACKED_BASE (0x114420e8) = 0x0
                 PCIEPORT::PCIE_CCIX_STACKED_LIMIT (0x114420ec) = 0x0
           PCIEPORT::PCIE_CCIX_DUMMY_RD_UPPER_ADDR (0x114420f0) = 0x0
           PCIEPORT::PCIE_CCIX_DUMMY_RD_LOWER_ADDR (0x114420f4) = 0x0
                 PCIEPORT::PCIE_CCIX_DUMMY_RD_CTRL (0x114420f8) = 0x4000
           PCIEPORT::PCIE_CCIX_DUMMY_WR_UPPER_ADDR (0x114420fc) = 0x0
           PCIEPORT::PCIE_CCIX_DUMMY_WR_LOWER_ADDR (0x11442100) = 0x0
                   PCIEPORT::PCIE_CCIX_MISC_STATUS (0x11442104) = 0x0
                 PCIEPORT::PCIE_P_PORT_LANE_STATUS (0x11442140) = 0x8
                               PCIEPORT::PCIE_FC_P (0x11442180) = 0x4001fc
                              PCIEPORT::PCIE_FC_NP (0x11442184) = 0x400000
                             PCIEPORT::PCIE_FC_CPL (0x11442188) = 0x20007c
                           PCIEPORT::PCIE_FC_P_VC1 (0x1144218c) = 0x20007c
                          PCIEPORT::PCIE_FC_NP_VC1 (0x1144218c) = 0x20007c
                         PCIEPORT::PCIE_FC_CPL_VC1 (0x11442194) = 0x0
                           PCIEPORT::PCIE_ERR_CNTL (0x114421a8) = 0x500
                            PCIEPORT::PCIE_RX_CNTL (0x114421c0) = 0x108c000
                 PCIEPORT::PCIE_RX_EXPECTED_SEQNUM (0x114421c4) = 0x31c
                 PCIEPORT::PCIE_RX_VENDOR_SPECIFIC (0x114421c8) = 0x0
                           PCIEPORT::PCIE_RX_CNTL3 (0x114421d0) = 0x0
             PCIEPORT::PCIE_RX_CREDITS_ALLOCATED_P (0x11442200) = 0xd20d1e
            PCIEPORT::PCIE_RX_CREDITS_ALLOCATED_NP (0x11442204) = 0x590000
           PCIEPORT::PCIE_RX_CREDITS_ALLOCATED_CPL (0x11442208) = 0x9102c2
             PCIEPORT::PCIEP_ERROR_INJECT_PHYSICAL (0x1144220c) = 0x0
          PCIEPORT::PCIEP_ERROR_INJECT_TRANSACTION (0x11442210) = 0x0
                       PCIEPORT::PCIEP_NAK_COUNTER (0x11442218) = 0x0
       PCIEPORT::PCIEP_RX_CAPTURED_LTR_CTRL_STATUS (0x11442220) = 0x0
  PCIEPORT::PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES (0x11442224) = 0x0
                            PCIEPORT::PCIE_LC_CNTL (0x11442280) = 0x40810030
                   PCIEPORT::PCIE_LC_TRAINING_CNTL (0x11442284) = 0x9400bcc0
                 PCIEPORT::PCIE_LC_LINK_WIDTH_CNTL (0x11442288) = 0xda880436
                      PCIEPORT::PCIE_LC_N_FTS_CNTL (0x1144228c) = 0x78ffc20c
                      PCIEPORT::PCIE_LC_SPEED_CNTL (0x11442290) = 0xfc788207
                          PCIEPORT::PCIE_LC_STATE0 (0x11442294) = 0x20212210
                          PCIEPORT::PCIE_LC_STATE1 (0x11442298) = 0x20212210
                          PCIEPORT::PCIE_LC_STATE2 (0x1144229c) = 0x20353637
                          PCIEPORT::PCIE_LC_STATE3 (0x114422a0) = 0x10202131
                          PCIEPORT::PCIE_LC_STATE4 (0x114422a4) = 0x90a0b0f
                          PCIEPORT::PCIE_LC_STATE5 (0x114422a8) = 0x3050608
              PCIEPORT::PCIE_LINK_MANAGEMENT_CNTL2 (0x114422ac) = 0x0
                           PCIEPORT::PCIE_LC_CNTL2 (0x114422c4) = 0x97184380
                  PCIEPORT::PCIE_LC_BW_CHANGE_CNTL (0x114422c8) = 0x100
                        PCIEPORT::PCIE_LC_CDR_CNTL (0x114422cc) = 0x1018060
                       PCIEPORT::PCIE_LC_LANE_CNTL (0x114422d0) = 0xfff0
                           PCIEPORT::PCIE_LC_CNTL3 (0x114422d4) = 0xa850b026
                           PCIEPORT::PCIE_LC_CNTL4 (0x114422d8) = 0x340078c
                           PCIEPORT::PCIE_LC_CNTL5 (0x114422dc) = 0x4020d45c
                     PCIEPORT::PCIE_LC_FORCE_COEFF (0x114422e0) = 0x80000
                PCIEPORT::PCIE_LC_BEST_EQ_SETTINGS (0x114422e4) = 0x28c0d414
              PCIEPORT::PCIE_LC_FORCE_EQ_REQ_COEFF (0x114422e8) = 0x1b280000
                           PCIEPORT::PCIE_LC_CNTL6 (0x114422ec) = 0x8a000090
                           PCIEPORT::PCIE_LC_CNTL7 (0x114422f0) = 0x12ee
             PCIEPORT::PCIE_LINK_MANAGEMENT_STATUS (0x114422f4) = 0x0
               PCIEPORT::PCIE_LINK_MANAGEMENT_MASK (0x114422f8) = 0x3fff
               PCIEPORT::PCIE_LINK_MANAGEMENT_CNTL (0x114422fc) = 0x12813
                          PCIEPORT::PCIEP_STRAP_LC (0x11442300) = 0x0
                        PCIEPORT::PCIEP_STRAP_MISC (0x11442304) = 0x27
                         PCIEPORT::PCIEP_STRAP_LC2 (0x11442308) = 0x0
                  PCIEPORT::PCIE_LC_L1_PM_SUBSTATE (0x11442318) = 0x4540000
                 PCIEPORT::PCIE_LC_L1_PM_SUBSTATE2 (0x1144231c) = 0x0
                      PCIEPORT::PCIE_LC_PORT_ORDER (0x11442320) = 0xc
                       PCIEPORT::PCIE_BCH_ECC_CNTL (0x11442340) = 0x100
                      PCIEPORT::PCIEP_HPGI_PRIVATE (0x11442348) = 0x40
                              PCIEPORT::PCIEP_HPGI (0x11442368) = 0x0
                   PCIEPORT::PCIEP_HCNT_DESCRIPTOR (0x1144236c) = 0x80000011
                           PCIEPORT::PCIE_LC_CNTL8 (0x11442374) = 0x400003
                           PCIEPORT::PCIE_LC_CNTL9 (0x11442378) = 0xf0ffe800
                    PCIEPORT::PCIE_LC_FORCE_COEFF2 (0x1144237c) = 0x80000
             PCIEPORT::PCIE_LC_FORCE_EQ_REQ_COEFF2 (0x11442380) = 0x0
   PCIEPORT::PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES (0x11442388) = 0x3
                          PCIEPORT::PCIE_LC_CNTL10 (0x1144238c) = 0x3f00003
                          PCIEPORT::PCIE_LC_CNTL11 (0x11442390) = 0xb0602000

This shows that the margin capabilities registers in the PCIECORE space are all zeros, which makes sense given the result of trying to margin the downstream of 40/3/3

      PCIECORE::PCIE_RXMARGIN_CONTROL_CAPABILITIES (0x114804d4) = 0x0
                PCIECORE::PCIE_RXMARGIN_1_SETTINGS (0x114804d8) = 0x0
                PCIECORE::PCIE_RXMARGIN_2_SETTINGS (0x114804dc) = 0x0

Contributor guide

No contributing guide indexed for this repository

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Reproduce the reported cases with /tmp/lmar, including the upstream and downstream commands for BDFs 40/3/3 and 48/0/0, then compare them with the /usr/lib/pci/pcieadm output. Review dumpregs.sh M2A and the listed PCIECORE registers; the issue does not define the expected downstream behavior, so clarify the intended result before considering the work complete.

Written by the indexing model from the issue text.

Assessment

Tech stack
rust
Domain
embedded-iot
Issue type
Bug
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
20/100

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