Consider a way to build bitfields during FPGA register codegen

Today we can generate Rust enums from enums encoded in the RDL. For registers which are just collections of single bit indicators, it would be nice to have a type that could be easily added to a ringbuf which would display the name of a bit and its status.

I am thinking something like the following RDL:

reg {
  name = "Example";

  field {
    desc = "Bit 1";
  } BIT1[1:1] = 0;

  field {
    desc = "Bit 0";
  } BIT0[0:0] = 0;
} EXAMPLE;

It would be nice to be able to get an Example type in the generated rust which could then be pretty-printed, e.g.: Example { Bit0: false, Bit1: false }

Start by locating the RDL register code-generation entry point and the generated Rust types. Compare the single-bit field example with existing enum generation, then define how the generated type should represent and pretty-print each bit's name and status for ringbuf use.