Add AArch64 SVE, SVE2 to simd-intrinsics
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enhancement
- Dominant language
- C
- Stars
- 13.6k
- Forks
- 2.6k
- PR merge metrics
- No merged PRs in 30d
Description
These are new Arm instruction set SIMD extensions, beyond NEON/ASIMD. Besides wider vectors, particularly relevant new instructions are 3-input XOR (EOR3), AND-NOT-XOR (BCAX), and XOR-rotate and rotate-XOR (XAR, RAX1).
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the existing simd-intrinsics support for NEON/ASIMD and understanding how instruction-set extensions are represented. Determine how AArch64 SVE and SVE2, including EOR3, BCAX, XAR, and RAX1, fit that structure; done means the requested extensions and instructions are supported.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- performance
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 30/100