Re-add support for AltiVec on pre-POWER8
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- Dominant language
- C
- Stars
- 13.6k
- Forks
- 2.6k
- PR merge metrics
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Description
Apparently, during the mass non-x86 SIMD work in GSoC 2015 we got extensive support for AltiVec as available on POWER8, but at the same time broke the more limited support we had (and still have in the core tree, for bitslice DES) for pre-POWER8 AltiVec. Due to Jim's recent work, we're now falling back to a fully non-SIMD build on POWER7 and below.
We should re-add support for AltiVec as available on pre-POWER8 CPUs, when building on/for those. Apparently, the most difficult aspect here is either defining a 64-bit SIMD add (for SHA-512) through 32-bit SIMD add and handling of the carry between odd and even 32-bit halves with extra intrinsics, or having just those formats that need this capability (thus, anything based on SHA-512) build without SIMD.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue names no files or tests. Begin by tracing existing AltiVec handling for bitslice DES and the POWER7/POWER8 build selection, then compare the SIMD paths and determine how SHA-512's 64-bit add is handled. Done means pre-POWER8 builds regain AltiVec where supported without breaking the non-SIMD fallback.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- performance
- Issue type
- Bug
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100