Support CIRCT's `seq` dialect

It would be nice to start being able to parse/represent some of CIRCT's [`seq` dialect](https://circt.llvm.org/docs/Dialects/Seq/).

A good start would be creating the dialect folder in `Veir/Dialects` and adding the `seq.clock` type and `seq.to_clock` and `seq.firreg` ops, to allow the below basic register circuit to be parsed with `veir-opt`. This can be run with `lake exe veir-opt input.mlir`

```mlir
"builtin.module"() ({
"hw.module"() <{comment = "", module_type = !hw.modty, parameters = [], per_port_attrs = [], result_locs = [loc(unknown)], sym_name = "top"}> ({
^bb0(%arg0: i1, %arg1: i1, %arg2: i1):
%0 = "seq.to_clock"(%arg0) : (i1) -> !seq.clock
%1 = "seq.firreg"(%arg2, %0) <{name = "q"}> : (i1, !seq.clock) -> i1
"hw.output"(%1) : (i1) -> ()
}) : () -> ()
}) : () -> ()
```

Further useful ops would be `seq.clock_inv` and `seq.shiftreg` that would let us parse:

```mlir
"builtin.module"() ({
"hw.module"() <{comment = "", module_type = !hw.modty, parameters = [], per_port_attrs = [], result_locs = [loc(unknown)], sym_name = "top"}> ({
^bb0(%arg0: i1, %arg1: i1, %arg2: i1):
%0 = "seq.to_clock"(%arg0) : (i1) -> !seq.clock
%1 = "seq.clock_inv"(%0) : (!seq.clock) -> !seq.clock
%2 = "seq.firreg"(%arg2, %1) <{name = "q"}> : (i1, !seq.clock) -> i1
"hw.output"(%2) : (i1) -> ()
}) : () -> ()
}) : () -> ()
```

```mlir
"builtin.module"() ({
"hw.module"() <{comment = "", module_type = !hw.modty, parameters = [], per_port_attrs = [], result_locs = [loc(unknown)], sym_name = "top"}> ({
^bb0(%arg0: i1, %arg1: i1, %arg2: i1):
%0 = "seq.to_clock"(%arg0) : (i1) -> !seq.clock
%1 = "hw.constant"() <{value = true}> : () -> i1
%2 = "seq.shiftreg"(%arg2, %0, %1) <{numElements = 1 : i64, operandSegmentSizes = array}> : (i1, !seq.clock, i1) -> i1
"hw.output"(%2) : (i1) -> ()
}) : () -> ()
}) : () -> ()
```