Question: Is it possible to access Altera FPGAs with Level-Zero?

Following the spec:
https://spec.oneapi.com/level-zero/latest/core/INTRO.html

Level-zero SPEC also works for spatial architectures.

When looking at the zeInit function (https://github.com/oneapi-src/level-zero/blob/master/include/ze_api.h#L567), the current implementation only supports GPU.

typedef enum _ze_init_flag_t
{
    ZE_INIT_FLAG_GPU_ONLY = ZE_BIT(0),              ///< only initialize GPU drivers
    ZE_INIT_FLAG_FORCE_UINT32 = 0x7fffffff

} ze_init_flag_t;

Are there any plans to include FPGAs?

Related to FPGAs, if I want Level-Zero and SPIRV, I guess I would need at least OpenCL 2.1? However, I see that the latest Quartus still implements OpenCL 1.0. Any plans on this front?

Thanks
Juan

Start by reading include/ze_api.h around zeInit and compare its GPU-only initialization flag with the Level-Zero specification linked in the issue. Review the FPGA and SPIR-V questions against the cited Quartus OpenCL 1.0 support; the issue currently provides no concrete implementation scope or completion criteria.