Consolidate cfg gate blocks in chipset device construction
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- Dominant language
- Rust
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- Merged PRs (30d)
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Description
During the i440bx host PCI bridge resourcification (#3331), reviewer feedback noted that the growing number of individual #[cfg(guest_arch = "x86_64")] blocks in chipset device construction code could be consolidated into fewer, larger blocks to reduce visual noise and improve readability.
This is a cleanup/refactor task — no behavioral change expected.
Areas to review
vmm_core/vmotherboard/src/base_chipset.rs— device deps constructionopenvmm/openvmm_core/src/worker/dispatch.rs— device handle emissionopenhcl/underhill_core/src/worker.rs— OpenHCL device construction
Context
As more x86-only devices get resourcified (ISA DMA, CMOS RTC, PIT, PIIX4, i440BX), each adds its own cfg gate. Merging adjacent gates into consolidated blocks would be cleaner.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Review the device construction code in vmm_core/vmotherboard/src/base_chipset.rs, openvmm/openvmm_core/src/worker/dispatch.rs, and openhcl/underhill_core/src/worker.rs. Start by comparing the adjacent #[cfg(guest_arch = "x86_64")] blocks in each area. Consolidate compatible gates while preserving the existing device dependencies and handles; done means cleaner grouping with no behavioral changes.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- operating-systems
- Issue type
- Refactor
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Clearly specified
- Newbie friendliness
- 72/100