microsoft / microsoft/microxcaling
using fp32 data format to simulate mx data format is not equivalent？
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- Dominant language
- Python
- Stars
- 364
- Forks
- 53
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Description
It's nice work but I have some questions：
we see that we use template T=float （see following code）
（1）to use fp32 to represent mx data format and
（2）simulating mx format calculation operation using fp32
so I think this may exist in-equivalent with real mx data format representation and operation. Do you use FPGA to evaluate how much error between the fp32-simuation and real mx data format？
template<typename T>
__global__ void quantize_mx_cuda_kernel(
const T* __restrict__ input,
const int scale_bits,
const int elem_ebits,
const int elem_mbits,
const float elem_max_norm,
const float* __restrict__ max_values,
const long total_size,
const int axis_size,
const int post_axis_size,
const bool flush_fp32_subnorms,
const RoundingMode rounding_mode,
T* __restrict__ output
) {
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Research direction
The issue points to the quantize_mx_cuda_kernel entry point but names no file or test. Trace its callers and determine how fp32 simulation is compared with MX-format behavior, then identify an evaluation path for the numerical error, including the FPGA comparison requested. Done means the equivalence or discrepancy is measured and documented with reproducible results.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp, python, pytorch
- Domain
- machine-learning, performance
- Issue type
- Bug
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100