<list>: Consider retuning the splice family to take advantage of Ice Lake and later store pairing
Nobody has claimed this yet.
- Dominant language
- C++
- Stars
- 11.1k
- Forks
- 1.7k
- Avg merge
- 4d 15h
- Merged PRs (30d)
- 22
Description
The September update of the Intel Architecture Optimization Manual is out: https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf
New in Ice Lake is the ability for the chip to fuse multiple stores to the same cache line so that they both occur in the same cycle. (Search for "store pairing" in the document.)
As a result it might make sense to rearrange the load and store sequence at https://github.com/microsoft/STL/blob/cd8fee03209d3312bf3c79abf81371290f116d84/stl/inc/list#L469-L488 to do all the stores to each list node edited together. We would need to test with a splice heavy benchmark like <xhash> rebucketing on different CPUs.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Read stl/inc/list around lines 469-488 and the linked Intel Architecture Optimization Manual section on store pairing. Benchmark the existing and any rearranged splice sequences using rebucketing on different CPUs. Done means the measurements establish whether the change benefits Ice Lake and later processors.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- performance
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 30/100