`<atomic>`: Distinguish load and store fence on ARM64
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- C++
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Description
arm has different barrier types for load and store barrier, for anything below acq_rel full barrier is superfluous.
Note that is is not fully superseded by #83, since there is atomic_thread_fence:
https://github.com/microsoft/STL/blob/12c684bba78f9b032050526abdebf14f58ca26a3/stl/inc/atomic#L169
https://github.com/microsoft/STL/blob/12c684bba78f9b032050526abdebf14f58ca26a3/stl/inc/atomic#L188-L190
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start in stl/inc/atomic at the referenced atomic_thread_fence implementation, then review the ARM64 fence handling and issue #83. Determine how load and store orderings below acq_rel should select their respective barrier types; done means atomic_thread_fence no longer uses a superfluous full barrier for those cases.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- performance
- Issue type
- Refactor
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100