[SPIR-V] 64-bit RWByteAddressBuffer atomic methods are unimplemented

Description

DXC's SPIR-V backend does not implement the Shader Model 6.6 64-bit RWByteAddressBuffer atomic methods. Compiling any shader that calls one of these methods through the SPIR-V codegen path fails with error: intrinsic 'Interlocked<Op>64' method unimplemented. The same shader compiles fine against the DXIL target. The affected methods are:

• RWByteAddressBuffer::InterlockedAdd64
• RWByteAddressBuffer::InterlockedAnd64
• RWByteAddressBuffer::InterlockedOr64
• RWByteAddressBuffer::InterlockedXor64
• RWByteAddressBuffer::InterlockedMin64
• RWByteAddressBuffer::InterlockedMax64
• RWByteAddressBuffer::InterlockedExchange64
• RWByteAddressBuffer::InterlockedCompareStore64
• RWByteAddressBuffer::InterlockedCompareExchange64

These methods are documented in the SM 6.6 64-bit and Float Atomics spec and are exercised by DXC's own DXIL test tools/clang/test/HLSLFileCheck/hlsl/intrinsics/atomic/atomicop_i64.hlsl. A code search for these symbols in tools/clang/lib/SPIRV returns zero hits.

Steps to Reproduce

test.hlsl:

RWByteAddressBuffer rb : register(u0);

[numthreads(1, 1, 1)]
void main() {
  uint64_t orig;
  rb.InterlockedOr64(0, (uint64_t)1);
  rb.InterlockedOr64(8, (uint64_t)1, orig);
}

Compile against DXIL (succeeds):

dxc.exe -T cs_6_6 -HV 202x test.hlsl

Compile against SPIR-V (fails):

dxc.exe -T cs_6_6 -HV 202x -spirv -fspv-target-env=vulkan1.3 test.hlsl

The same failure reproduces for InterlockedAnd64, InterlockedAdd64, InterlockedXor64, InterlockedMin64, InterlockedMax64, InterlockedExchange64, InterlockedCompareStore64, and InterlockedCompareExchange64.

Actual Behavior

SPIR-V compilation fails with:

test.hlsl:7:6: error: intrinsic 'InterlockedOr64' method unimplemented
  rb.InterlockedOr64(0, (uint64_t)1);
     ^
test.hlsl:8:6: error: intrinsic 'InterlockedOr64' method unimplemented
  rb.InterlockedOr64(8, (uint64_t)1, orig);
     ^

Expected behavior: the SPIR-V backend lowers each Interlocked<Op>64 method to the corresponding OpAtomic* instruction on a uint64_t view of the buffer, declaring the Int64Atomics capability and SPV_KHR_shader_atomic_int64 extension as needed.

Additional observation (possibly related): on the same SPIR-V target, 64-bit InterlockedOr against groupshared int64_t / uint64_t counters compiles and runs to completion but leaves every accumulator at its initial value -- regular stores from thread 0 are visible in the output buffer, but every InterlockedOr on groupshared 64-bit memory produces no observable effect. This is consistent with the emitted SPIR-V either lacking the Int64Atomics capability / SPV_KHR_shader_atomic_int64 extension, or selecting a non-atomic instruction, and may share a root cause with the missing RWByteAddressBuffer methods above.

Environment

• DXC version: <[!-- output of 'dxc --version' --](dxcompiler.dll: 1.10(5354-7284bb18)(1.9.0.15354) - 1.9.0.15354 (main, 7284bb180-dirty))>
• Host Operating System: Windows

Start by reproducing the failure with the provided HLSL and SPIR-V command, then inspect tools/clang/lib/SPIRV and compare the affected methods with tools/clang/test/HLSLFileCheck/hlsl/intrinsics/atomic/atomicop_i64.hlsl. Verify all listed 64-bit RWByteAddressBuffer atomics lower successfully and that the required Int64Atomics capability and SPV_KHR_shader_atomic_int64 extension are emitted where needed.