microsoft / microsoft/DirectXShaderCompiler
[SPIR-V] 16-bit stores emit 32-bit stores with masking
Nobody has claimed this yet.
- Dominant language
- C++
- Stars
- 3.7k
- Forks
- 900
- Avg merge
- 2d 11h
- Merged PRs (30d)
- 44
Description
Description
DXC generates 32-bit store op with masking for a 16-bit store into a RWByteAddressBuffer. This is functionally correct for a single thread, but broken fundamentally when multiple lanes access adjacent memory to modify, i.e. lane0's higher WORD would be lane1's lower WORD.
Steps to Reproduce
HLSL example: https://godbolt.org/z/W1sxM63ro
Command line: dxc -T cs_6_6 -E main -enable-16bit-types -spirv -HV 2021 -fvk-use-scalar-layout -fcgl
Actual Behavior
The GLSL example below shows in SPIR-V how 16-bit store would instead be generated correctly.
https://godbolt.org/z/vjMqj83Gf
Environment
- DXC version: Trunk
- Host Operating System: Windows 11
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reproducing the HLSL example with the listed dxc command and compare its SPIR-V output with the GLSL result in the linked Godbolt examples. Trace the SPIR-V code-generation path for RWByteAddressBuffer 16-bit stores; done means adjacent lanes can update neighboring 16-bit values without the emitted 32-bit masked store causing interference.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 38/100