Continuous assignment from argumentless functions

This is a dedicated location to discuss a potential addition to the style guide to cover the following edge case:

VCS (2020.12) will currently not run this correctly:

module test;

function automatic [7:0] test_func;
    test_func = 1;
endfunction

wire [7:0] test_wire = test_func();

initial begin
    #1;
    $display("Expected %h, Recieved %h", test_func(), test_wire);
    // Will fail because test_func() is never run
    $finish;
end

endmodule

Possible solutions

This is a summary of the discussion made in #66.

• Disallow calling of functions from assign/wire. always_comb should be used instead. By @sifferman and @marnovandermaas
• Disallow all wire assignments during declaration, (wire [7:0] test = test_func()). By @GregAC
• Disallow argumentless functions. By @nbdd0121

Full explanation by @GregAC in https://github.com/lowRISC/style-guides/issues/66#issuecomment-1662118280

I think I'd prefer to outright ban wire [7:0] test = test_func() type statements. This is because their semantics varies depending upon the net type. For wire you do get the equivilent to a continuous assignment but for logic it's just an initial value setting (much like an initial block though not identical! Those initial assignments are made before any initial blocks are run). Switching wire to logic may otherwise appear innocuous so better to avoid the complexity altogether. I note we explicitly allowed this currently:

https://github.com/lowRISC/style-guides/blob/5cd912c617c712c773fdc9da9259298d183a2da9/VerilogCodingStyle.md?plain=1#L2702-L2725

Initial assignments can be useful in FPGA but are deadly for ASIC synthesis as it's a great way to get simulation/synthesis mismatch where the FPGA version agrees with the simulation but the ASIC synthesis doesn't. If you confine them to an 'initial block at least it makes it far obvious you have one. We could consider saying initial blocks are only allowed in RTL that is strictly for FPGA usage (e.g. top-levels and wrappers etc that we may use on FPGA to instantiate IP)

Start with the discussion in issue #66 and the linked VerilogCodingStyle.md section referenced in this issue. Compare the proposed rules for function calls and declaration-time wire assignments, then determine which policy the style guide should state. Done means the guide contains an agreed, unambiguous rule covering the shown SystemVerilog example.