[sv] How to format module instantiations that fit in a single line?

Nobody has claimed this yet.

In the SystemVerilog style guide, should we *require* module instantiations which fit on a single line to do so? (We're trying to come down to a single way of formatting certain constructs, so this question is either-or.)

Option 1:
```
and2 my_gate (.out_o(sig_output), .in1_i(first_input), .in2_i(second_input));
```
vs

Option 2:
```
and2 my_gate (
.out_o(sig_output),
.in1_i(first_input),
.in2_i(second_input)
);
```

We already prefer (or allow) the use of Option 1 in other occasions, so it would be consistent with that (e.g. https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#begin--end).

I guess the main use case would be the instantiation of SV modules modeling gates, clock buffers, or other tiny modules.

@hzeller Is this something Verible has an opinion on right now?

CC @mdhayter @eunchan @msfschaffner @tomroberts-lowrisc @dsandrs @GregAC @rswarbrick @sriyerg @mwbranstad

(Split out from #48)

Review the SystemVerilog section of VerilogCodingStyle.md, especially the existing guidance linked around begin/end formatting, and read the discussion on this issue. Determine whether a single-line rule should be adopted for compact module instantiations, then document the decided option and its scope in the style guide.

Written by the indexing model from the issue text.