Use of SystemVerilog Interfaces

This guide lists SV interfaces as [problematic](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#problematic-language-features-and-constructs) and that their use is discouraged. Do you have a specific rationale for this?

My own experience is that SV Interfaces are invaluable for verification code, and _can_ be used for RTL as long as care is taken with synthesis. I do not know if SV Interfaces are supported by all FPGA synthesis tools (its been a while since I've tried that).

Read VerilogCodingStyle.md at the “problematic language features and constructs” section, then review the issue discussion about SystemVerilog interfaces and synthesis support. Done means the guide’s rationale is documented or its guidance is revised, but the issue does not specify which outcome is expected.

Written by the indexing model from the issue text.