lowRISC / lowRISC/style-guides

[SystemVerilog] Create style guide torture test

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Description

It would be nice to have a "parser torture test" for our SV style guide: a synthesizable design which uses all the features we're using in our style guide. We can then use this to quickly check if tools are able to understand our SV subset. Essentially, copying all code examples into a couple files ...

I'd not go beyond a parser test, i.e. it's out of scope if the tool actually understands and processes the constructs right.

The need for this showed up in https://github.com/lowRISC/ibex/issues/117. (Quartus Standard doesn't support some of the constructs we're using.)

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Review the SystemVerilog style guide examples and the context in lowRISC/ibex issue 117 first. Collect the examples into a couple of synthesizable parser-test files, then check that the intended tools can parse them; semantic support for the constructs is explicitly out of scope.

Written by the indexing model from the issue text.

Assessment

Domain
testing
Issue type
Feature
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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