RV32E support
Open
Nobody has claimed this yet.
arch-support
clang
llvm
- Dominant language
- Shell
- Stars
- 277
- Forks
- 55
- PR merge metrics
- No merged PRs in 30d
Description
This RISC-V base ISA supports only 16 registers. Some details of the ABI plus calling convention change as well. The LLVM side shouldn't be complex, but the definition of the psABI For RV32E seems to be somewhat behind RV32G/RV64G.
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the LLVM-side RV32E support and the RISC-V psABI, comparing RV32E with RV32G/RV64G. Done means the 16-register ISA and its ABI and calling-convention differences are supported consistently; the issue names no files or tests, so the scope must be established first.
Written by the indexing model from the issue text.
Assessment
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100