[syn] Check with tool vendors how out of range enum assignments / casts are synthesized

Spun out from #9391. We want to check how synthesis tools treat casts from a logic vector to an enum variable of the same size, e.g.:
```systemverilog
parameter int MuBi4Width = 4;
typedef enum logic [MuBi4Width-1:0] {
MuBi4True = 4'hA, // enabled
MuBi4False = 4'h5 // disabled
} mubi4_t;

logic [MuBi4Width-1:0] inputval;
mubi4_t enumvar;

assign enumvar = mubi4_t'(inputval);
```
In particular, we are interested in how this cast behaves if `inputval` is not within the defined enum range (i.e., not `MuBi4True` nor `MuBi4False` in this example).

We basically want to make sure that the casts do not get synthesized into a "filter" that collapses invalid encodings into one value.

Start with the SystemVerilog example in the issue and test casts from a logic vector to an enum using the relevant synthesis tools or tool vendors. Done means documenting whether out-of-range encodings are preserved or collapsed by synthesis, including the behavior for values other than MuBi4True and MuBi4False.

Written by the indexing model from the issue text.