[fpga] Enhance ast model to also include adc functions

@Jacob-Levy is already working on this.

Since Sep 20, 2021.

now that ast is integrated in fpga, we can look into wrapping the adc functions as well.
Below is a snippet of code from @mdhayter on how he enabled this for a prototype.

```
## XADC Header
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS12 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS12 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS12 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS12 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]

/// ADC HACK STARTS HERE DO NOT CHECK IN
logic xadc_eoc, xadc_dready;
logic [15:0] xadc_data;
logic [6:0] xadc_addr;
logic [15:0] adc_din0, adc_din1, adc_val;
wire [15:0] aux_channel_p;
wire [15:0] aux_channel_n;
wire [7:0] alm_int;
assign alarm_out = alm_int[7];
assign aux_channel_p[0] = xa_p[0];
assign aux_channel_n[0] = xa_n[0];

assign aux_channel_p[1] = xa_p[1];
assign aux_channel_n[1] = xa_n[1];

assign aux_channel_p[2] = 1'b0;
assign aux_channel_n[2] = 1'b0;

assign aux_channel_p[3] = 1'b0;
assign aux_channel_n[3] = 1'b0;

assign aux_channel_p[4] = 1'b0;
assign aux_channel_n[4] = 1'b0;

assign aux_channel_p[5] = 1'b0;
assign aux_channel_n[5] = 1'b0;

assign aux_channel_p[6] = 1'b0;
assign aux_channel_n[6] = 1'b0;

assign aux_channel_p[7] = 1'b0;
assign aux_channel_n[7] = 1'b0;

assign aux_channel_p[8] = 1'b0;
assign aux_channel_n[8] = 1'b0;

assign aux_channel_p[9] = 1'b0;
assign aux_channel_n[9] = 1'b0;

assign aux_channel_p[10] = 1'b0;
assign aux_channel_n[10] = 1'b0;

assign aux_channel_p[11] = 1'b0;
assign aux_channel_n[11] = 1'b0;

assign aux_channel_p[12] = 1'b0;
assign aux_channel_n[12] = 1'b0;

assign aux_channel_p[13] = 1'b0;
assign aux_channel_n[13] = 1'b0;

assign aux_channel_p[14] = 1'b0;
assign aux_channel_n[14] = 1'b0;

assign aux_channel_p[15] = 1'b0;
assign aux_channel_n[15] = 1'b0;
// pulled from wizard in vivaldo
XADC #(
.INIT_40(16'h0000), // config reg 0
.INIT_41(16'h21AF), // config reg 1 cont seq, calibrate, alarms off
.INIT_42(16'h0200), // config reg 2 clk/2 (50MHz->25MHz)
.INIT_48(16'h0000), // Sequencer channel selection
.INIT_49(16'h0003), // Sequencer channel selection
.INIT_4A(16'h0000), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
.INIT_50(16'hB5ED), // Temp alarm trigger
.INIT_51(16'h57E4), // Vccint upper alarm limit
.INIT_52(16'hA147), // Vccaux upper alarm limit
.INIT_53(16'hCA33), // Temp alarm OT upper
.INIT_54(16'hA93A), // Temp alarm reset
.INIT_55(16'h52C6), // Vccint lower alarm limit
.INIT_56(16'h9555), // Vccaux lower alarm limit
.INIT_57(16'hAE4E), // Temp alarm OT reset
.INIT_58(16'h5999), // VCCBRAM upper alarm limit
.INIT_5C(16'h5111) // VCCBRAM lower alarm limit
) xadc_inst (
.CONVST(GND_BIT),
.CONVSTCLK(GND_BIT),
.DADDR(xadc_addr),
.DCLK(clk_i),
.DEN(xadc_eoc),
.DI(16'b0),
.DWE(1'b0),
.RESET(~rst_ni),
.VAUXN(aux_channel_n[15:0]),
.VAUXP(aux_channel_p[15:0]),
.ALM(),
.BUSY(),
.CHANNEL(),
.DO(xadc_data),
.DRDY(xadc_dready),
.EOC(xadc_eoc),
.EOS(),
.JTAGBUSY(),
.JTAGLOCKED(),
.JTAGMODIFIED(),
.OT(),
.MUXADDR(),
.VP(1'b0),
.VN(1'b0)
);

always @ (negedge xadc_dready or negedge rst_ni) begin : proc_adc
if (!rst_ni) begin
adc_din0 <= 0;
adc_din1 <= 0;
xadc_addr <= 7'h10;
end else begin
case (xadc_addr[3:0])
4'h1: adc_din0 <= xadc_data;
4'h0: adc_din1 <= xadc_data;
endcase

case(xadc_addr)
7'h11: xadc_addr <= 7'h10;//last address goes out and load new address in
7'h10: xadc_addr <= 7'h11;
default: xadc_addr <= 7'h10;
endcase // case (xadc_addr)
end // else: !if(!rst_ni)
end
assign adc_val = usb_frame[10] ? adc_din1 : adc_din0;
```