[reggen] Add support for compact regwen_multi type
- Dominant language
- SystemVerilog
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- 2d 22h
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Description
Right now, if a multireg needs to use regwen, it takes one of two forms.
1. All multi registers are locked with the same regwen
2. Each multi register is locked with a separate regwen. In this case, both the reg and regwen have to be non-compact multi-regs.
While 2 works fine, it creates more burden on the software to have to manage multiple sets of registers.
Add an option to support compact multireg regwen in the future.
To do this, when creating multiregs, we need to have some idea of attributes of the regwen (whether its compact or not). It may be better then to have reg_block.py do a 2 pass loop over registers. First to identify all the regwens and figure out their attributes, and the second pass as it is today. This will then give all the registers some structure to directly fetch regwen attributes.
We can't do this today because by the time the multireg class starts creating registers, we are already way beyond the point of getting any information on the regwen attributes. In fact, we do not validate regwen attributes until after all registers are created.
This is probably a longer term goal since it also has a sizeable impact on DV
Contributor guide
Research direction
Start in reg_block.py and follow the multireg creation path, including where regwen attributes are validated. Determine how a two-pass register walk could expose compact and non-compact regwen attributes before multireg registers are created; done means compact regwen_multi is accepted with the required attribute handling and validation remains correct.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- python
- Domain
- tooling
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100