Standardize all FIFOs in OpenTitan

Nobody has claimed this yet.

Many of our blocks (such as uart, I2C, spi_device, spi_host, csrng etc) contain one or more FIFOs, which support some of following features.

1. FIFO status: Size, watermark, empty, full, overflow, underflow, read/write pointer, idle
2. Interrupts: watermark, empty, full, overflow, underflow
3. FIFO operations: FIFO reset

Request a design enhancement to create a standardized FIFO wrap to support all these features with parameters that can enable/disable the supports. And use this wrapper in all the design. Here are some rationales:

1. Simplify the IP-level verification and reduce DV effort.
It's very time consuming to verify these FIFO features in block-level testbench, especially if we want to model the FIFO behaviors in scoreboard to test them thoroughly. If we standardize it, we could have a standalone TB to verify the FIFO and only do integration test in IP-level as well as excluding code coverage of the FIFO

2. Have consistent behavior and naming.
We already have different names for FIFO watermark in our IPs. In Uart, we define watermark to be edge-triggered interrupt. Since we don't standardize it, it's possible that some other designers define it as a level-triggered interrupt in their block.

Include DV folks. @rasmus-madsen @rswarbrick @senelson7 @sriyerg @matutem @cindychip @udinator

Start by inventorying the FIFO implementations in the uart, I2C, spi_device, spi_host, and csrng blocks and compare their status, interrupt, and reset behavior. Define the standardized wrapper and its configurable features with the DV stakeholders, then confirm that the affected blocks use it consistently and that standalone FIFO verification covers the supported behavior.

Written by the indexing model from the issue text.