lowRISC / lowRISC/opentitan

RFC: CSRs for Prims

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#7,688 7 comments 0 reactions 1 assignee Assigned to @msfschaffner View on GitHub
Component:RTL Earlgrey-PROD Triaged Priority:P2 RFC:Approved
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SystemVerilog
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Description

Some comportable IPs (OTP, Flash) have primitives with CSRs nodes. These CSRs are macro-specific and typically (but not only) DFT / test related. Currently these CSRs are defined in a separate Hjson located in a closed repo, maintained by the Silicon Creator.

![image](https://user-images.githubusercontent.com/41358501/128945813-d197fbb3-06f7-4569-8c7c-495c4af76251.png)

This creates problems with our design and DV tooling, since these tools do not understand the concept of "nested CSR" nodes. For example, the DV environment generates RAL models for both `reg_top 1` and `reg_top 2` in the picture above, and these RAL models alias onto each other, which causes problems with both automated and directed tests.
Furthermore, the crossbar configuration (offset / size) for these CSRs is not inferred correctly by the design and DV tooling.

There are several potential approaches to this problem and discussions on how to solve this are currently ongoing.
However, it is clear that a change (either on the DV, tooling or design side) is going to be necessary.
This issue serves as a place holder until we have converged on a solution.

See also [these slides](https://docs.google.com/presentation/d/19XZXqM4AF94y6FMtbfVaqQjlps-Rp5-tHQN7pkuW7I4/edit) for an overview of the solutions considered so far.

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