[dv/sw] add an address in the `fake` simulation SRAM region
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Component:DV
Earlgrey-PROD Triaged
Type:Enhancement
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- SystemVerilog
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Description
From this comment:
https://github.com/lowRISC/opentitan/pull/7270/files#r679609071
The proposal plans to have a more robust way to sync between sw and dv event.
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