[reg] Correct HW write behavior for shadow writes

Reference #7632

The basic question is exactly how shadow registers should behave when it is written by hardware.
While we could stick with the two write rule, this potentially complicates the race condition handling when software / hardware collide. It also seems...."weird".

It's not completely clear right now what such a use case would even be. Ie, shadow registers are really meant for scenarios where a multi-bit value is provided from software to hardware, and we want to ensure its effect stays the same. A hardware write "most likely" would be hardware providing some kind of status / data to software. If this value were faulted, in most cases it should not have a backwards effect on hardware, so there isn't a clear need for shadow going HW -> SW.

If the purpose of the HW is really to clear something because an operation has completed, then it doesn't really seem like a two-write approach is right either.

In any case, the above PR disables the shadow / hardware-write case and we will revisit if anyone finds an actual usecase.

Start with referenced issue #7632 and the earlier PR mentioned in this issue, which disables shadow writes from hardware. No file or test is named; first establish the intended hardware-write semantics and race behavior, then identify the affected RTL and tests. Done requires an agreed behavior implemented and verified for the relevant shadow-write cases.