[top] update documentation
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- SystemVerilog
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Description
Update `top_earlgrey/doc/_index.md` with relevant top level information. Such as
- [ ] how alert escalation is handled
- [ ] how sram execution is handled (mention main vs retention SRAM differences #8969)
- [ ] what modules are connected for wakeup / reset request
- [ ] how life cycle relates to strap and how that is hooked up at the top level
- [x] updated memory map
- [ ] what modules are always on
- [ ] integrity scheme
- [ ] clock relationships #6798
This list goes on and i'm sure there are more. Please add to this list if you think of more.
Effectively this will be like documenting and explaining `top_earlgrey.hjson`
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with top_earlgrey/doc/_index.md and compare it with top_earlgrey.hjson to identify missing top-level explanations. Work through the checklist, including alert escalation, SRAM execution, wakeup/reset modules, lifecycle and straps, always-on modules, integrity, and clock relationships. Done means the relevant top-level information is documented and the checklist reflects the remaining gaps.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation, embedded-iot
- Issue type
- Documentation
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100