[Verilator] Split top_*_verilator into testbench and chip-level module

Split out from https://github.com/lowRISC/opentitan/issues/5221.

- [x] Split the Verilator top into a Verilator chip-level module (with padring and etc.) and a separate Verilator testbench. (#7544)
- [x] Template the Verilator chip-level module
- [ ] Re-enable Verilator JTAG DPI

Start by reading the parent issue #5221 and the completed split tracked in #7544 to understand the Verilator chip-level module and testbench boundaries. Then trace the remaining Verilator JTAG DPI path; done means JTAG DPI is re-enabled and the Verilator testbench and chip-level module still work together.

Written by the indexing model from the issue text.