[verilator] Bypass or speed up UART for logging

In Verilator simulations we currently use the UART peripheral and the uartdpi BFM to transfer log messages from device software to the user. This approach is rather slow, with a single line of text in a `LOG_INFO()` call taking easily 50k simulated cycles, which at 10 kHz simulation speed results in 5 seconds wall-clock simulation time.

I didn't profile further where the slowdown really comes from, some of it will be from `printf()` processing, a bit of slowdown is by design (transferring a single character should take around 7200 baud/125 kHz = 17 cycles).

The same of course applies to production software, however, 50k cycles easily go unnoticed at higher clock frequencies, e.g on FPGA builds.

We need to see where the slowdown actually comes from, and then either fix it, or (if no other way can be found) switch the Verilator simulation to use a approach similar to what DV logging is using.

Start by profiling the Verilator UART path, including the uartdpi BFM and printf() processing, to identify where the 50k simulated cycles are spent. Done means either the slowdown is fixed or Verilator logging uses an approach similar to DV logging, with improved log-message simulation time.

Written by the indexing model from the issue text.