[CI] Add USB tests to FPGA CI
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Component:CI
Earlgrey-PROD Triaged
IP:usbdev
Priority:P2
- Dominant language
- SystemVerilog
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- 2d 22h
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Description
Add tests to CI which utilize the USB peripheral on an FPGA board. See also https://github.com/lowRISC/opentitan/pull/4330
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