[top_englishbreakfast] Follow-up tasks for auto-generated top-levels

Since #4329 we now have basic support for different top-level configurations and a second top-level called `top_englishbreakfast`. For this top-level we mainly check in the hjson config files. All the auto-generated sources are generated at build time through FuseSoC. Some parts of the framework are far from perfect if not horribly ugly but we needed to move on to unblock the SCA work and get ready for future additions to the top-level that will definitely outgrow the NexysVideo FPGA board.

In the process of the PR review, rebase, and debug we came across several points that need to be investigate/solved in the future. The purpose of this issue is to track those points.

Documentation:
- [x] See e.g. [slides available on the OT team drive](https://docs.google.com/presentation/d/1JAgAIbFCAA3hwLcCcwWJiXy6wyIQNmdx7HaSuQGXGZQ/edit#slide=id.p).

Project:
- [x] Define how to proceed with `top_earlgrey`/`top_jasmine` as the NexyisVideo becomes too small. Most likely, the NexysVideo will no longer be the main platform and the corresponding top-level will become a secondary configuration. Most of the CI and DV resources will be focused on the main platform. See also #5397. It has been decided to drop support for the NexysVideo, see #7814 .
- [x] Define up to which level we are going to support differences in the various top-levels. We are not going to support more differences near term to focus our effort on more critical things.

Software:
- [ ] Find a better and cleaner way to build software for different top-levels. See also #5397

Hardware:
- [x] Add support for a bigger FPGA board and switch over to that for main development platform. See also #5397, see #6614
- [x] Cleanup of old and no longer used/usable Earl Grey targets: `top_earlgrey_cw305`, `top_earlgrey_artys7-50`

Tooling
- [ ] Find a better way to deal with multiple implementations of the same core in FuseSoC. We are currently using `fileset_x` flags but this is not a scalable and long-term solution.
- [ ] Allow topgen to generate software only, or register files only, see #4512
- [ ] Add lint support for secondary top-levels (dvsim would need to call the FuseSoC generator for that).

CI:
- [ ] Add the ChipWhisperer CW305 FPGA board to the lowRISC CI center and perform an AES test capture in CI.
- [x] Execute a "hello world" on the English Breakfast Verilator simulation in CI. See #7582

This is related to #295 .

Begin by reviewing the unchecked Software, Tooling, and CI items, then read the referenced issues #5397 and #4512 alongside the existing top-level and FuseSoC configuration. Choose one concrete follow-up and define completion as the requested build, generation, lint, or CI behavior working for the affected top-levels.

Written by the indexing model from the issue text.