[dv] investigate ALL #delay waits with DV testbench
Open
Component:DV
Earlgrey-PROD Candidate
Priority:P3
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
From PR #4282 Sri recommended to investigate all #delay waits and see if we can replace with something better.
I will start to look into them from common DV functions to each IP.
Contributor guide
Research direction
Start with the common DV functions, then review the #delay waits across each IP in the DV testbench. Inventory the waits and determine which can be replaced with an alternative. Done means the full set of waits has been investigated and replacement decisions are documented or implemented.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100