[asserts] Different assert disable condition for clocks
Open
Component:DV
Earlgrey-PROD Candidate
IP:clkmgr
Milestone:V3
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
For known output asserts in clocking modules, see [here](https://github.com/lowRISC/opentitan/pull/4015), the clocks technically should be known even before the reset release.
There should be a different condition for these specific cases other than reset.
> estimate 12
Contributor guide
Assessment
This issue has not been assessed yet.