lowRISC / lowRISC/opentitan

[verilator] File upstream bug about the simulation segfaulting with tracing enabled and binds in code

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#3,951 2 comments 0 reactions 0 assignees View on GitHub
Component:Tooling Earlgrey-PROD Triaged Priority:P3
Dominant language
SystemVerilog
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Description

When running a Verilator simulation with `--trace` to get a FST trace the simulation segfaults. This happens with both Verilator 4.040 and the latest master version.

A git bisect shows commit d052f1c0f6cfd026a1d7c2b3fd1ef360a94d0a0e ([verilator] Update to use sim SRAM area for exit) triggering the segfault (merged in https://github.com/lowRISC/opentitan/pull/3782).

Backtrace:

```
Simulation running, end by pressing CTRL-c.
Tracing enabled.
Writing simulation traces to sim.fst

Thread 1 "Vtop_earlgrey_v" received signal SIGSEGV, Segmentation fault.
fstWriterEmitValueChange (ctx=0x1c53440, handle=4294967295, val=val@entry=0x7ffffffd0590) at /home/philipp/swinstall/verilator/share/verilator/include/gtkwave/fstapi.c:2934
2934 len = vm4ip[1];
(gdb) bt
#0 fstWriterEmitValueChange (ctx=0x1c53440, handle=4294967295, val=val@entry=0x7ffffffd0590) at /home/philipp/swinstall/verilator/share/verilator/include/gtkwave/fstapi.c:2934
#1 0x0000000000433604 in VerilatedFst::emitIData (bits=, newval=, code=, this=)
at /home/philipp/swinstall/verilator/share/verilator/include/verilated_fst_c.cpp:233
#2 VerilatedTrace::fullIData (this=, oldp=, newval=, bits=)
at /home/philipp/swinstall/verilator/share/verilator/include/verilated_trace_imp.cpp:532
#3 0x0000000000b3f026 in Vtop_earlgrey_verilator::traceFullSub0 (userp=0x7ffff797b040, tracep=0x1c4d1f0) at Vtop_earlgrey_verilator__Trace__4__Slow.cpp:14406
#4 0x0000000000b31d3f in Vtop_earlgrey_verilator::traceFullTop0 (userp=0x7ffff797b040, tracep=0x1c4d1f0) at Vtop_earlgrey_verilator__Trace__4__Slow.cpp:12934
#5 0x000000000043344d in VerilatedTrace::dump (this=0x1c4d1f0, timeui=)
at /home/philipp/swinstall/verilator/share/verilator/include/verilated_trace_imp.cpp:444
#6 0x0000000000410aaf in VerilatorSimCtrl::Run (this=this@entry=0x1c2a140 )
at ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilator_sim_ctrl.cc:281
#7 0x0000000000410c3d in VerilatorSimCtrl::RunSimulation (this=0x1c2a140 )
at ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilator_sim_ctrl.cc:129
#8 0x0000000000410cf1 in VerilatorSimCtrl::Exec (this=this@entry=0x1c2a140 , argc=argc@entry=6, argv=argv@entry=0x7fffffffd0a8)
at ../src/lowrisc_dv_verilator_simutil_verilator_0/cpp/verilator_sim_ctrl.cc:48
#9 0x000000000040858b in main (argc=6, argv=0x7fffffffd0a8) at ../src/lowrisc_systems_top_earlgrey_verilator_0.1/top_earlgrey_verilator.cc:39
```

I'll keep trying to narrow down the problem a bit more. Fortunately, the relevant commit isn't large.

Contributor guide

Open the contributing guide

Research direction

Reproduce the simulation with Verilator and `--trace`, using the bind configuration described in the issue. Start with `verilated_fst_c.cpp`, `verilated_trace_imp.cpp`, and the bisected commit d052f1c0f6cfd026a1d7c2b3fd1ef360a94d0a0e; done means narrowing the failure enough to file an upstream bug with the reproduction, bisect result, and backtrace.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
tooling
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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