[i3c] Miscellaneous implementation issues
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Description
### Description
This issue collates a few implementation issues that are not related to the design of the IP block or implementation of the specifications, mostly at the level of the physical design, e.g. DFT or clock buffers.
- [ ] Top-level DFT scan signals need address, and the impacted clock gates and RAMs inspected/addressed.
- [ ] i3c_input_buffers uses a regular buffer `i3c_buf_en` for the SDA, rather than a clock gate; is this okay/sufficiently-well matched.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the top-level DFT scan signals and the impacted clock gates and RAMs, then inspect i3c_input_buffers and its i3c_buf_en SDA buffer. Confirm which implementation issues require changes and document completion when the scan paths and buffer choice have been reviewed and addressed.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100