lowRISC / lowRISC/opentitan

[i3c] Error detection and handling in the Controller

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#31,305 0 comments 0 reactions 1 assignee Claimed by @alees24 View on GitHub
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Description

### Description

Error detection, handling and reporting (likely to be somewhat open ended):

- CE0:1,3 obviously.
- Overflow conditions when hardware-written buffers are full.
- Reporting of correct byte counts when a write is aborted.
- Reporting of CRC mismatch, parity mismatch.
- CCC handling is incomplete in various ways w.r.t. error detection, reporting and recovery.
- Briefly: Controller FSM is inconsistent in rejecting new rxbuf/ibi read data (ca. i3c_controller_fsm:1145). It could also be slightly more forgiving in permitting simultaneously acceptance of the previous word and capture of new data.

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