[i3c] I3C Controller incompleteness

### Description

Features to be ratified:
- DAT cache has just ended up mirroring the entire DAT; this could therefore be simplified, once proven.

Features still to be implemented:

- Abort, Suspend and Resume of Command handling has been deferred.
- Handling of MIPI Internal Control Commands (HCI).
- Dynamic Address Assignment; needs completing. ENTDAA has previously been demonstrated in an immature form, but CCC handling moved on. SETDASA may be considered untested and incomplete too.
- RSTACT/Target Reset handling requires completion; it shall involve use of the critical section and issuing of more than a simple pattern.
- Issuing of DISEC after rejection of an In-Band Interrupt.
- Negotiation in HDR-DDR signaling (ENDXFER).
- Controller should issue periodic traffic automatically to ensure that passive Hot-Join/IBI Targets can communicate.

Deferred; not yet decided whether they shall be implemented later:
- Auto-Command behavior.
- Combo Transfer commands.