For SiVal test cases, test is running relevant FPGA or silicon regression
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- SystemVerilog
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Description
This issue has no description.
Contributor guide
Research direction
The issue body does not identify any files, tests, or regression entry points. First clarify which SiVal test cases are affected and whether FPGA or silicon regression is expected, then document the specific test entry point and observable behavior that would count as fixed.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100