[chip-test]
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Component:ChipLevelTest
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Test point name
More
Host side component
Rust
OpenTitanTool infrastructure implemented
Yes
Silicon Validation (SiVal)
Yes
Emulation Targets
- #31246
- #31247
- #31248
Contact person
No response
Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- #31239
- #31240
- #31241
- #31242
- #31243
- #31244
- #31245
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue names no source files or tests; start by reviewing linked issues #31239–#31248 and the Rust host-side chip-test context. Done is represented by completing the listed checklist and emulation targets, which are already checked.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- rust
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Active
- Clarity
- Needs clarification
- Newbie friendliness
- 15/100