[sram_ctrl,dv] sram_ctrl_csr_mem_rw_with_rand_reset sometimes fails

Nobody has claimed this yet.

### Description

Running 16 iterations with the retention RAM configuration sees two failures with f81a9bd881.
```
## SRAM_CTRL/RET Simulation Results
### Thursday August 27 2026 07:29:59 UTC
### GitHub Revision: [`f81a9bd881`](https://github.com/lowrisc/opentitan/tree/f81a9bd881363c11acad9d6e03a4e0ff1718d733)
### Branch: tmp
### [Testplan](https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html)
### Simulator: XCELIUM

### Test Results

| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|:-------:|:--------------------------:|:-------------------------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 11.000s | 10004.494us | 14 | 16 | 87.50 % |
| V1 | | **TOTAL** | | | 14 | 16 | 87.50 % |
| | | **TOTAL** | | | 14 | 16 | 87.50 % |

## Coverage Results
### [Coverage Dashboard](/home/rjs/work/opentitan/scratch/tmp/sram_ctrl_ret-sim-xcelium/cov_report/index.html)

## Failure Buckets
* `UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *` has 1 failure:
* Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failure.
* 8.sram_ctrl_csr_mem_rw_with_rand_reset.103155406910593662364765057380729829754673004340876161639316385417269121305050\
Line 113, in log /home/rjs/work/opentitan/scratch/tmp/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

UVM_INFO @ 34602475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

* `UVM_FATAL (sram_ctrl_base_vseq.sv:177) [sram_ctrl_common_vseq] Timed out waiting for initialization done` has 1 failure:
* Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failure.
* 10.sram_ctrl_csr_mem_rw_with_rand_reset.99793776235139478956637282210435885689538148485828349091671293593418921300604\
Line 105, in log /home/rjs/work/opentitan/scratch/tmp/sram_ctrl_ret-sim-xcelium/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

UVM_INFO @ 10004494351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

```

Start by rerunning sram_ctrl_csr_mem_rw_with_rand_reset with the retention RAM configuration and inspect the two failing run logs. Read csr_utils_pkg.sv:463 for the scr_key_rotated.success mismatch and sram_ctrl_base_vseq.sv:177 for the initialization timeout. Done means repeated iterations complete without either failure bucket.

Written by the indexing model from the issue text.