lowRISC / lowRISC/opentitan

[rv_dm,dv] rv_dm_rom_read_access test failure

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Component:DV IP:rv_dm
Dominant language
SystemVerilog
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Description

### Description

This V1 test is failing with the error:
```
UVM_ERROR @ 47690944 ps: (rv_dm_scoreboard.sv:409) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected response to read from address 0xac851800 in mem reg block. Problems: '{"Expected read d_data=0, but it was 0x180006f"}. Item: (req: (cip_tl_seq_item@23599) { a_addr: 'hac851800 a_data: 'h46d4258b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h27ca5 d_param: 'h0 d_source: 'h33 d_data: 'h180006f d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd13 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
```

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First steps

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  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start with the V1 rv_dm_rom_read_access test and the failure reported at rv_dm_scoreboard.sv:409. Reproduce the test and inspect the read at address 0xac851800, which returns 0x180006f instead of the expected 0. Done means the test passes with the expected read response.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, testing-qa
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Active
Clarity
Needs clarification
Newbie friendliness
35/100

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