[otbn,dv] Fix BadDeepLoop generator in OTBN RIG
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Description
The OTBN random instruction generator (RIG) can fail more often than expected to generate a BadDeepLoop snippet. This snippet should trigger a loop error because the "programmed" loop is invalid. The RIG fails here because it cannot find an invalid loop configuration given the try limit.
This snippet should be improved to reduce false positive failures in the regressions. This is an artifact from the memory increase, see https://github.com/lowRISC/opentitan/pull/29318.
Contributor guide
Research direction
Start with the OTBN random instruction generator and its BadDeepLoop snippet, then review the memory-increase context in pull request 29318. The work is done when the snippet still triggers the invalid programmed-loop error while reducing false-positive regression failures caused by the try limit.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100