[i3c] Open points in Target transceiver

Start/Restart/Stop detectors

The logic to detect Start/Restart/Stop conditions in the Target transceiver has currently a few shortcomings that make it not very robust and problematic for one case:

• If a START is immediately followed by a STOP (legal according to Spec), the detected STOP is sticky and never cleared, leading to concurrently detected START and STOP conditions.
• If the address header after a START contains no ones, it lacks a rising edge on SDA which however is the only way to clear the STOP detection signal (which is still asserted from the previous frame). Although this should be fixed as well, the only address header which fulfills this conditions is the all-zeros one, i.e., I3C address 0 in write access. I3C address 0, however, is a reserved one and shall not be used.

HDR Traffic Handling

• ddr_mode only becomes asserted only after the first SCL posedge in HDR-DDR mode. Discussion
• PRE0 of every Read Data Word is driven push-pull, but should be released at C1 rising edge. Discussion1 Discussion2
• hdr_exit_det_i is sampled on the very edge that asynchronously resets it. Discussion
• There is currently no address checking for DDR read commands: Both not being addressed as well as not having read data available pushes the FSM into the not-yet implemented State_TxNACKDDR. This causes unintended partial transfers for both ordinary read transfers addressed to other Targets and for read transfers addressed to us that cannot be served. Discussion
• HDR-DDR CCC framing is not yet supported. The pre-existing traces in the code caused CCC transfers to be misinterpreted as private transfers and vice versa. This has now been stubbed and a TODO added. Discussion
• HDR ENDXFER options; nack, early termination, CRC transmission after Abort.

General / Miscellaneous

• Driving is currently not released on certain abnormal frame termination conditions. Discussion
• The CCC FSM should be refactored. Since it tracks both CCC and Private transfers, a more general naming would be accurate. Furthermore, all of its rather complex state calculation logic, plus the same for the sequential trans structure, is currently in the else branch of the sequential process of the respective flops.

Start with the Target transceiver's Start/Restart/Stop detectors, HDR-DDR handling, and CCC FSM described in the issue, then read the linked pull request discussions for context. Done means resolving the listed detection, framing, release, address-checking, ENDXFER, and FSM issues, with the checklist fully addressed.