[i3c] Target transceiver reset generation
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- SystemVerilog
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Description
Description
The asynchronous reset signal for the Target transceiver logic is currently generated from flops clocked in the main system domain, followed by combinatorial logic. See targ_trx_rst_n driven by i3c_timers.sv in i3c_core.sv.
This must be changed: Reset signal must come from a flop and either
- the reset signal get synchronized to all consumer clocks
- or made sure through logic that the reset signal only asserts and releases when none of the consumer clocks is active
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing targ_trx_rst_n from i3c_timers.sv into i3c_core.sv, including the consumer clocks mentioned in the issue. Determine whether synchronization or gated assertion and release best fits the target transceiver logic. Done means the reset is flop-generated and cannot assert or release while a consumer clock is active, with the affected RTL behavior verified.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 52/100